A Unified Programmable Edge Matrix Processor for Deep Neural Networks and Matrix Algebra

Matrix Algebra and Deep Neural Networks represent foundational classes of computational algorithms across multiple emerging applications like Augmented Reality or Virtual Reality, autonomous navigation (cars, drones, robots), data science, various artificial intelligence-driven solutions. An accelerator-based architecture can provide performance energy efficiency supporting fixed functions through customized paths. However, constrained Edge systems requiring diverse matrix operations to be efficiently supported, cannot afford numerous custom accelerators. In this article, we present MxCore, a unified that comprises tightly coupled vector programmable cores sharing highly optimized interconnects along with configurable hardware scheduler managing the co-execution. We submit MxCore as generalized approach facilitate flexible acceleration Deep-learning range sparsity levels. Unified compute resources improve overall resource utilization per unit area. Aggressive novel microarchitecture techniques block-level support optimize data-reuse minimize bandwidth power requirements enabling ultra-low latency for low-power cost-sensitive deployments. requires small silicon footprint 0.2068 mm 2 , in modern 7-nm process at 1 GHz achieves (0.15 FP32 0.62 INT8) TMAC/mm dissipating only 11.66 μW leakage power. At iso-technology iso-frequency, provides an 651.4×, 159.9×, 104.8×, 124.2× compared 128-core Nvidia’s Maxwell GPU dense General Multiply, sparse Network, Cholesky decomposition, triangular solve respectively.